1. Field of the Invention
The present invention relates to a notebook personal computer with a display apparatus, and particularly to a display apparatus having a display panel and a driving circuit board for driving the display panel. Also, the present invention relates to a flexible printed circuit film for connecting the display panel with the driving circuit board.
2. Description of the Prior Art
Generally, the display apparatus used in notebook computer (hereinafter “NTPC”) is composed of the display panel having a pixel (picture element) matrix and panel driving circuits for driving the display panel. The panel driving circuits drive the pixel matrix so that picture information processed in a central processing unit (hereinafter “CPU”) is displayed on the display panel. Actually, the display apparatus for the NTPC includes a liquid crystal panel 10, a plurality of row drivers 12 and a plurality of source drivers 14, as shown in FIG. 1. The liquid crystal panel 10 includes the pixel matrix formed between two glass substrates (not shown). The row drivers 12 drive sequentially row lines GL of the pixel matrix, and the source drivers 14 perform a function of supplying data signals to the column lines CL of the pixel matrix. In the display apparatus, a timing control board 16 is provided to receive signals from a graphic control board 18 included in a NTPC body 20. The graphic control board 18 converts graphic data into video data to be adaptable for displaying on the liquid crystal panel. The video data consists of red (hereinafter “R”), green (hereinafter “G”) and blue (hereinafter “B”) data. These R, G and B data are applied to the source drivers 14 through a first flexible printed circuit film (hereinafter “FPC film”) 11, the timing control board 16 and a data bus 13. The graphic control board 18 also generates a main clock signal, a vertical synchronous signal and a horizontal synchronous signal to be supplied via the first FPC film 11 to the timing control board 16. The timing control board 16 generates timing signals for controlling the timing of the row and source drivers 12 and 14 on the basis of the main clock signal, vertical and horizontal synchronous signals. The timing signals are supplied to the row and source drivers 12 and 14 through control lines 15. In addition to the timing signals, the timing control board 16 generates panel voltage signals such as a common voltage signal and so on, gamma compensation voltage signals, and high and low voltage signals for a gate pulse. The gamma compensation voltage signals are applied to the source drivers 14, the high and low voltage signals are supplied to the row drivers 12. The panel driving voltage signals are transmitted to the liquid crystal panel 10, row and source drivers 12 and 14. To this end, in the timing control board 16 includes a timing control circuit chip for performing the data interface and the timing control, a gamma compensation voltage generating circuit for generating the gamma compensation voltage, a scan voltage generating circuit for generating the high and low voltage signals, and a power supply for generating the panel driving voltage signals.
In case of adapting the display apparatus having such circuitry structure to the NTPC, the graphic control board 18 is mounted on a main printed circuit board (hereinafter “MPCB”) of a NTPC body 20, and the display panel 10, the row and source drivers 12 and 14, and the timing control board 16 are provided to a panel module 22 separated from the NTPC body 20. The panel module 22 further includes a back light unit 24 for irradiating lights to the liquid crystal panel 10 and a back light driver 26 for driving the back light unit 24.
The back light driver 26 responds to signals from the MPCB through second FPC film 17 and generates an AC (alternative current) voltage signal to be applied to back light unit 24 through a voltage signal line 19, responding to the light control signal LCS. To this end, the back light driver 26 consists of a chopper 30, inverter 32, transformer 34, and coupling capacitor C1 connected serially between the second FPC film 17 and a back light lamp 28, and a lamp current detector 36 and a brightness controller 38 coupled electrically to the chopper 30. The chopper 30 switches the DC (Direct Current) voltage signal Vbl to be supplied from the second FPC to the inverter 32 in accordance with a light control signal LCS from the second FPC film 17. Also, the chopper 30 adjusts the voltage level of the DC voltage signal responding to output signals of the lamp current detector 36 and brightness controller 38. The inverter 32 converts the DC voltage signal from the chopper 30 into the AC voltage signal, and the transformer 34 boosts the AC voltage signal from the inverter 32. The AC voltage signal boosted by the transformer 32 is applied to the back light lamp 28 through the coupling capacitor C1. The coupling capacitor C1 blocks out a DC component included in the boosted AC voltage signal. The coupling capacitor C1 and the lamp current detector 36 are connected to the back light lamp 28 by the voltage signal line 19 shown in FIG. 1.
Also, the panel module 22 having the circuitry structure as described above, is formed in the shape as shown in FIGS. 3A and 3B. In the FIGS. 3A and 3B, the NTPC body 20 is provided with a main housing 20A having the MPCB 20B. The MPCB 20B has the graphic control board 18 fixed thereon. The panel module 22 includes the liquid crystal panel 10, third and fourth FPC films 21 and 23. The liquid crystal panel 10 is provided with the timing control board 16, row and source drivers 12 and 14, and back light driver 26. The row drivers 12 and source drivers 14 are arranged at the left and bottom edges of the upper surface of the liquid crystal panel 10, respectively. The timing control board 16 coupled electrically with the graphic control board 18 by the first FPC film 11 is positioned at the left edge of the lower surface of the liquid crystal panel 10. The third FPC film 21 connects the timing control board 16 with the row and source drivers 12 and 14. To this end, the third FPC film 21 consists of the data bus 13 and the control lines 15 as shown in FIG. 1. The back light driver coupled electrically with the MPCB 22B by the second FPC film 17 is positioned at right side of the liquid crystal panel 10. The voltage line 19 connects the back light driver 26 with the back light unit 24 (not shown).
In the display apparatus as above mentioned, since the graphic control board 16 and the timing control board 18 are arranged in NTPC apart from each other, the R, G and B data, the synchronous signals and the clock signal are greatly affected by noise. Due to this, the picture displayed by the conventional display apparatus will be correspondingly distorted.
To minimize the influence of noise, a low noise display apparatus as shown in FIG. 4, is provided with a low noise display apparatus having a scanning transmitter 40 and a scanning receiver 42. The scanning transmitter 40 is positioned in the NTPC body 20 to be connected between the graphic control board 18 and the first FPC film 11, while the scanning receiver 42 is disposed in the panel module 22 to be connected between the first FPC film 11 and the timing control board 16. The graphic control board 18 is connected to the MPCB of the NTPC body 20 through a computer interface bus 20C. The graphic control board 18 receives the graphic data processed by the MPCB and generates the R, G and B data, the main clock signal, and the vertical and horizontal synchronous signals to be applied to the scanning transmitter 40. The scanning transmitter 42 encodes the signals from the graphic control board 18 into a specific format of signals which are not affected by noise. The specific format signals encoded by the scanning transmitter 40 is supplied via the first FPC film 11 to the scanning receiver 42. The scanning receiver 42 decodes the specific format signals from the scanning transmitter 40 and recovers the R, G and B data, which are applied to the source drivers 14 through the timing control board 16. The timing control board 16 generates the timing control signals to be transmitted to the row and source drivers 12 and 14, on the basis of the main clock signal, the vertical and horizontal synchronous signals from the scanning receiver 42. It is to be understood that the detailed description regarding to the timing control board 18, liquid crystal panel 10, row and source drivers 12 and 14, back light unit 24 and back light driver 26 can be indicated by the previously disclosed FIG. 1. In the low noise display apparatus having the scanning transmitter and receiver 40 and 42, there is no apparent distortion of picture as the signals transmitted from the graphic control board 18 to the timing control board 16 are not affected by noise.
In the NTPC with the low noise display apparatus, the panel module 20 is pivotally secured at the rear edge on the top portion of the NTPC body 20, as shown in FIGS. 5 and 6. Referring to FIGS. 5 and 6, the NTPC body 20 includes a main housing 20A loaded with the MPCB 20B, and a keyboard 20C. Arranged On the MPCB 20B included in the NTPC body 20, are the graphic control board 18 and the scanning transmitter 40. In the panel module 22, a panel housing 22A is provided with the back light unit 24, liquid crystal panel 10 and a window frame 22B composed in multi-layers. The liquid crystal panel 10 consists of a lower and upper glass substrates 10A and 10B and a pixel matrix 10C between the lower and upper glass substrates 10A and 10B. The lower glass substrate 10A is provided with the row and source drivers 12 and 14 and the third FPC film 21 for connecting the drivers 12 and 14 with an printed control board 44. The row drivers 12 are arranged on the left edge of the surface of the lower glass substrate 10A, the source drivers 14 are positioned on the bottom edge of the surface of the lower glass substrate 10A. The printed control board 44 has the timing control board 16 and the scanning receiver 42 connected with the first FPC film 11. The timing control board 16 drives the row and source drivers 12 and 14 responding to the signals from the scanning receiver 42. The scanning receiver 42 transmits the signals from the first FPC film 11 to the timing control board 16. The printed circuit board 44 with the timing control board 16 and scanning receiver 42, is mounted by the third FPC film 21 between the back light unit 24 and the bottom surface of the panel housing 22A. The first FPC film 11 connects the scanning receiver 42 with the scanning transmitter 40 disposed on the MPCB 20B of the NTPC body 20. Further, in the panel module 20, the back light driver 26 secured at right side of the lower glass substrate 10A is provided with the second FPC film 17. The back light driver 26 applies the AC voltage signal via the voltage line 19 to the back light unit 24 responding to the light control signal from the second FPC film 17. The second FPC film 17 connects the back light driver with the MPCB 22B of the NTPC body 20.
In the low noise display apparatus as described the above, since the timing control board 16 and the scanning receiver 42 are mounted on the panel module 22, the panel module is thick and the number of elements and contacts are large. As a result, the construction and fabricating process of the display apparatus are complex and the reliability of the display apparatus drops off. Also, in the display apparatus, the effective screen area is small and the FPC film is complex, because the back light driver is positioned at the right side of the liquid crystal panel.